System for collecting data from meters placed at remote places

ABSTRACT

A data collection system wherein a central or data collection station is interconnected through data transmission lines with a plurality of meters or terminal stations at remote places and prior to the data reading operation a high-level voltage is applied from the central station to charge the stray capacitance between the data transmission lines and ground and thereafter a predetermined voltage is applied for reading data.

BACKGROUND OF THE INVENTION

The present invention relates to a data collection system forautomatically reading electric, water or gas meters in remote places tocollect data as to electric, water or gas quantities consumed for apredetermined period.

A prior art system which is related to the present invention will bedescribed with reference to FIG. 1. A central or data collection stationhas a circuit 1 for controlling relays for selecting counters. Forinstance, a control signal is transmitted through counter-selectionlines C_(R1) and C_(R2) to energize a coil of a relay R₁ to close acontact R_(1b). Thereafter, a counter-reading control circuit 2 isoperated to impress a predetermined voltage on a transmission line L₁ sothat a current flows through the line L₁, a least-significant-digitcontact A₁₁ of a counter M₁, a counter resister R₁, the relay contactR_(1b), a common transmission line L₀ and a detecting resistor R_(D).Counter resistors R₀ through R₉ of the counter M₁ have different valuesso that a value of the current flowing through the above circuit changesdepending upon the position of the counter contact A₁₁ and is detectedin terms of a voltage drop across the detecting resistor R_(D) by avoltage detecting circuit 3. In this case, the least-significant-digitof the counter M₁ is 1. In like manner, the control circuit 2 impressesa predetermined voltage on a transmission line L₂ to read the nextleast-significant digit or second digit. Since a second-digit contactA₂₁ is connected to a resistor R₀, the second digit is 0. In likemanner, the third digit and the fourth digit or most significant digitmay be read out and displayed by a display device 4. In this case,reading of the counter M₁ results 0901.

In the prior art system of the type described, each of a plurality oftransmission lines has stray capacitance so that when the controlcircuit 2 impresses a predetermined voltage on, for instance, thetransmission line L₁, the latter is charged to stray capacitance C₁within a relatively very short time as the transmission line L₁ has arelatively small resistance. After this stray capacitance C₁ has beencharged, the common transmission line L₀ is charged through the counterresistor R₁ to a stray capacitance C₀. In general, the counter resistorsR₀ through R₉ have high values ranging from 1K ohms to 10K ohms. Becausethe common transmission line L₀ is charged through one of these highresistance it takes a considerably long time before a voltage dropcorresponding to that across the counter resistor R₁ is derived acrossthe detecting resistor R_(D). As a result, the control circuit 2 must beoperated with a relatively long switching time sufficient to permit thecharging of the common transmission line L₀ to C₀ so that high-speeddata collection cannot be accomplished.

SUMMARY OF THE INVENTION

In view of the above, one of the objects of the present invention is toprovide a data collection system which may eliminate the above problemso that the data collection speed may be substantially increased.

Another object of the present invention is to provide a data collectionsystem which includes a very simple circuit which may permit thecharging of the common transmission line to its stray capacitance withina very short time so that the reading time may be considerably reducedand erroneous reading may be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS:

FIG. 1; 1a; b is a circuit diagram of a prior art data collectionsystem;

FIG. 2; 2a; b is a circuit diagram of a first embodiment of the presentinvention;

FIG. 3 shows electric waveforms used for the explanation of the mode ofoperation of the first embodiment;

FIG. 4; 4a; b is a circuit diagram of a second embodiment of the presentinvention;

FIGS. 5 and 6 show electric wave forms used for the explanation of themode of operation of the second embodiment; and

FIG. 7; 7a; b is a circuit diagram of a third embodiment of the presentinvention.

Same reference numerals are used to designate similar parts throughoutthe figures.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment, Figs. 2 and 3

As shown in FIG. 2, in each terminal station a series circuit consistingof a voltage control element such as a zener diode Z_(D1) and a resistorR₀₁₁ is interconnected between the data transmission line L₁ and thecounter contact R_(1b). The resistor R₀₁₁ has a value sufficientlysmaller than those of the counter resistors R₀ through R₉, but it may beeliminated when the transmission line L₁ has a sufficiently highresistance.

Next with further reference to FIG. 3, the mode of operation of thefirst embodiment will be described. At time t₁ the relay control circuit1 energizes the relay coil R₁ to close the relay contact R_(1b) (SeeFIG. 3-a) as with the prior art system shown in FIG. 1. Next as shown atFIG. 3-b, the control circuit 2 selects the transmission line L₁ andimpresses on it a voltage high enough to enable zener diode Z_(D1) toconduct. Because this voltage is high and the zener diode Z_(D1)exhibits a relatively small resistance, the common data transmissionline L₀ may be immediately charged to the stray capacitance C₀. Becausethe data transmission line L₁ has a relatively very small resistance,the charging time thereof to the stray capacitance C₁ presents noproblem at all. Next at t₂ the control circuit 2 impresses on the datatransmission line L₁ a detecting voltage which is constant and lowerthan a zener or breakdown voltage of the zener diode Z.sub. D1 (See FIG.3-c). Then, because the data transmission lines L₀ and L₁ have beenalready charged, a voltage drop corresponding to the voltage drop acrossthe counter resistor R₁ immediately appears across the detectingresistor R_(D), is detected by the voltage detecting circuit 3 and isdisplayed by or stored in the display or memory device 4. In likemanner, the control circuit 2 sequentially selects and impresses apredetermined voltage on the data transmission lines L₂, L₃ and L₄, sothat the second digit, the third digit and the most significant digitmay be sequentially read out at a relatively very small interval (SeeFIGS. 3-d, -e and -f) because the common data transmission line L₀ hasbeen already charged to its stray capacitance C₀ through the zener diodeZ_(D1). Depending upon the position of the counter contact the straycapacitance must be recharged by the defecting voltage, but a timerequired for recharging the stray capacitance of the common datatransmission line L₀ is negligible because the stray capacitance hasbeen already charged.

After all of the digits of the representation of the counter M₁, therelay control circuit 1 de-energizes the coil R₁ and then energizes acoil R₂ of a relay in the next terminal station at t₆, and the datareading control circuit 2 impresses a relatively high voltage on thedata transmission line L₁ (See FIG. 3-h) to charge the common datatransmission line L₀ to its stray capacitance C₀. Thereafter, therepresentation of the counter M₂ is read out by digit in the same manneras described above.

Second Embodiment, FIGS. 4, 5 and 6

In the second embodiment shown in FIG. 4, in each terminal station inaddition to the data transmission line L₁, other data transmission linesL₂, L₃ and L₄ are connected through zener diodes Z_(D2), Z_(D3) andZ_(D4), respectively, and resistors R₀₂₁, R₀₃₁ and R₀₄₁, respectively,to the counter contact R_(1b), so that a relatively high-level voltageis impressed on each data transmission line prior to the reading of eachdigit and consequently a reading speed may be considerably increased.

In operation, the relay control circuit 1 energizes the relay coil R₁ ofthe first terminal station (See FIG. 5-a), and then the data-readingcontrol circuit 2 impresses a gate voltage G₁ to a gate of a transistorTr₁ of the data transmission line L₁ to enable it to conduct (See FIG.5-b). Simultaneously, a switch SW₁ is closed to impress a high-levelvoltage to a circuit consisting of the data transmission line L₁, thezener diode Z_(D11), the resistor R₀₁₁, the counter contact R_(1b) andthe common data transmission line L₀ so that the data transmission lineL₁ and the common data transmission line L₀ are charged to theirrespective stray capacitance C₁ and C₀. Next a switch SW₂ is closedsimultaneous with the opening of the switch SW₁ so that a predeterminedlow-level voltage is impressed on the transmission line L₁. A voltageacross the detecting resistor R_(D), which is representative of thevoltage across the counter resistor R₁ is derived by a sampling puls SP₁and stored in a memory 5. Thereafter, the data-reading control circuit 2closes the gate of the transistor Tr₁ while impressing a gate voltage G₂to a gate of a transistor Tr₂ to enable it to conduct (See FIG. 5-c).Next the switch SW₁ is closed to impress a high-level voltage on acircuit consisting of the data transmission line L₂, the zener diodeZ_(D21), the resistor R₀₂₁, the counter contact R_(1b) and the commondata transmission line L₀ so that the data transmission line L₂ and thecommon data transmission line L₀ are charged to their respective straycapacitance C₂ and C₀. Thereafter, the switch SW₁ is opened while theswitch SW₂ is closed to impress a low-level voltage on the datatransmission line L₂ so that a voltage across the defecting resistorR_(D), which is representative of a voltage across the counter resistorR₀ is derived by the sampling puls SP₂ and stored in the memory 5. Inlike manner, the third digit and the fourth or most significant digitare read out and stored, and the relay control circuit 1 de-energizesthe relay coil R₁ while energizing the relay coil R₂ of the nextterminal station. In this way, respective terminal stations are sampledsequentially.

Next the reason why high-speed reading is possible in the secondembodiment shown in FIG. 4 will be described in detail. Because of thelow resistance L_(r1), L_(r2), L_(r3) and L_(r4) of the datatransmission lines itself, even with a low-level voltage the straycapacitance C₁, C₂, C₃ and C₄ of the data transmission lines may becharged within a relatively short time to their respective straycapacitance but it is clear that when a high-level voltage is impressedas described previously, they may be charged more rapidly. However, thisis not the main object of the second embodiment. The main object is torecharge, prior to each reading or sampling of digits, the common datatransmission line L₀ having a relatively long time constant which isdetermined by the stray capacitance C₀ and the value of one of thecounter resistors R₀ through R₉ each having a high value.

The mode of operation of the second embodiment will be described in moredetail with further reference to FIG. 6. As described previously, whenthe switch SW₁ is closed, a highlevel voltage V₁ (See FIG. 6-b) issupplied to the stray capacitance C₀ of the common data transmissionline L₀ through the transistor Tr₁, the data transmission line L₁, thezener diode Z_(D11) and the relay contact R_(1b) so that the straycapacitance C₀ is charged to V₀ (See FIG. 6-a). Therefore, at thisinstant the voltage across the detecting resistor R_(D) is equal to V₀.When the switch SW₁ is opened, the charge stored in the straycapacitance C₀ is rapidly discharged through R_(D) simultaneously withthe opening of the switch SW₁ so that a low-level voltage V₂ (See FIG.6-c) is supplied through the counter resistor R₁ so that the dischargeof the stray capacitance C₀ is prevented and a current having amagnitude dependent upon the value of the counter resistor R₁ flowsthrough the detecting resistor R_(D) so that a voltage v₁ correspondingto the value of the counter resistor R₁ appears across the detectingresistor R_(D). This voltage v₁ is sampled (See FIG. 6-e) by thesampling pulse SP₁ (See FIG. 6-d) and stored in the memory 5. Thus, thefirst or least significant digit "1" of the data represented by thecounter M₁ is stored.

Next the gate of the transistor Tr₁ is closed while the gate of thetransistor Tr₂ is opened and the switch SW₁ is closed to supply thehigh-level voltage V₁ to a circuit consisting of the data transmissionline L₂, the zener diode Z_(D21) and the common data transmission lineL₀ so that the stray capacitance is immediately recharged to V₀ from v₁.Thereafter, the switch SW₁ is opened while the switch SW₂ is closed sothat the low-level voltage V₂ is impressed through the counter resistorR₀ to the detecting resistor R_(D) and consequently a voltage v₂corresponding to the resistance of the counter resistor R₀ ; that is ,the second digit is derived across the detecting resistor R_(D). Thesecond digit, which is "0" in this embodiment, is sampled by a samplingpulse SP₂ and stored. In like manner, voltages v₃ and v₄ representingthe third and fourth digits, respectively, or the values of the counterresistors R₉ and R₀ may be derived and stored.

When the high-level voltage V₁ were not used, as with the case of thefirst embodiment shown in FIG. 2, for recharging the common datatransmission line L₀ to the stray capacitance C₀ prior to each readingfrom the second digit, it would take a considerably long time to chargefrom v₂, which is a relatively low voltage, to the high voltage v₃ whena digit represented by the counter resistor R₉ having a relatively highresistance is to be read out after a digit represented by the counterresistor R₀ having a relatively low resistance. As a result, the readingspeed is decreased. In each digit reading, there is a chance that aftera digit has been read out through the counter resistor R₀ having thelowest resistance, a digit must be read out through the counter resistorR₉ having the highest resistance. Therefore, the whole read time isfurther delayed. In this respect, the second embodiment shown in FIG. 4has a distinct advantage over the first embodiment shown in FIG. 2 inthat reading speed is far faster.

Third Embodiment, FIG. 7

The third embodiment shown in FIG. 7 is substantially similar inconstruction to the second embodiment shown in FIG. 4 except that thetransmission lines L₁, L₂, L₃ and L₄ are connected through the zenerdiodes and resistors to the common data transmission line L₀ at the endsof the data transmission lines instead of being connected through eachterminal station. Therefore, the capital cost may be considerablyreduced because of the elimination of the zener diodes in each terminalstation. Furthermore, the mode of operation is substantially similar tothat of the second embodiment so that high-speed reading may be assured.

So far delay in reading due to the stray capacitance of the common datatransmission line L₀ has been described, but the counter-selectionsignal transmission lines C_(rl) through C_(rm) have also straycapacitance C₅ through C_(m+4) so that delay in reading occurs becauseof delay in response of counter selection relays R₁ through R_(n). Toovercome this problem, a zener diode is connected in parallel with eachrelay coil as shown in FIGS. 2, 4 and 7, and is impressed with arelatively high-level voltage by the relay control circuit 1 so that thecounter selection signal transmission line may be immediately charged toits stray capacitance prior to the energization of the relay coil. Thusthe response of the relays R₁ through R_(n) may be considerablyimproved.

What is claimed is:
 1. In a data collection system of the typecomprising a plurality of counter-meters installed at remote places, adata collection station for reading data from said countermeters, aplurality of transmission lines interconnected between saidcounter-meters and said data collection station and comprising onecommon data transmission line and a plurality of other data transmissionlines equal in number to the number of digits of each counter-meter,each counter-meter having a plurality of resistors equal in number tothe number of digits of the counter-meter, each resistor being coupledbetween the corresponding counter-meter and one of said transmissionlines to indicate a value at a corresponding digit position, said datacollection station including means for sequentially sampling saidcounter-meters to read and collect the data of each counter-meterthrough said transmission lines,the improvement comprising: a voltagethreshold element interconnected between said common data transmissionline and each of said other data transmission lines corresponding toeach digit to be read out, said voltage threshold element beingconnected in parallel with said resistors of each counter-meter, saidthreshold element exhibiting a dynamic impedance substantially less thanthat of each of said resistors when subjected to a predeterminedhigh-level voltage, and a resistance substantially greater than that ofeach of said resistors when subjected to a predetermined low-levelvoltage, means for applying said high-level voltage between said commondata tranmission line and a selected one of said other data transmissionlines to cause a relatively high current to flow through said voltagethreshold element to charge stray capacitance between said common datatransmission line and said selected other data transmission line andbetween each of said lines and ground, and means for thereafter applyingsaid predetermined low-level voltage between said selected datatransmission line and said common data transmission line to causecurrent to flow through a corresponding one of said resistors of saidcounter-meter so that the corresponding digit value may be determined atsaid station.
 2. A data collection system as set forth in claim 1wherein other voltage threshold elements are interconnected between thecommon data transmission line and each of the remaining datatransmission lines so that prior to each digit reading the straycapacitance between said common data transmission line and each otherdata transmission line and between each of said lines and ground may becharged.
 3. A data collection system as set forth in claim 1 whereinsaid voltage threshold element is a zener diode.
 4. A data collectionsystem according to claim 2, wherein said voltage threshold elements areinterconnected between said common data transmission line and the datatransmission lines at the ends of said data transmission lines remotefrom said station.
 5. A data collection system according to claim 1,wherein installed adjacent to each of said counter-meters is a relayhaving a coil connected through relay-control signal transmission linesto said data collection station, said station including means forselecting and energizing the coil of the relay of a desiredcounter-meter to select said desired counter-meter for data reading, avoltage threshold element being connected in parallel with the coil ofeach relay, means for applying said predetermined high-level voltageacross said voltage threshold element to charge the stray capacitance ofthe relaycontrol signal transmission lines, and means for thereafterapplying said low-level predetermined voltage to energize the coil ofthe relay.